First Nvidia Blackwell wafer produced at TSMC Phoenix fab
Nvidia and Taiwan Semiconductor Manufacturing Company produced the first Nvidia Blackwell wafer on US soil at TSMC’s Phoenix facility in mid-September 2026, marking the formal start of volume manufacturing for Nvidia’s flagship artificial intelligence accelerator at TSMC Arizona. The wafer, fabricated on advanced process nodes, represents the first time a Blackwell-class chip has been completed end-to-end inside the United States.
Why the Nvidia Blackwell wafer milestone matters for US chip supply
The announcement, made during the week of September 15, 2026, carries strategic weight beyond ceremonial significance. Nvidia CEO Jensen Huang attended the event alongside TSMC executives, underscoring the partnership’s role in anchoring advanced AI compute capacity in Arizona. Both companies framed the milestone as a critical step toward diversifying the US semiconductor supply chain at a moment when AI hardware demand is straining global fab capacity. The Phoenix site joins a small and growing list of US facilities capable of producing leading-edge logic for hyperscale AI customers.
From a process technology standpoint, the achievement is substantial. TSMC Arizona will run the Blackwell wafer through a portfolio of advanced nodes, including the 2-nanometer, 3-nanometer, and 4-nanometer processes, alongside the A16 chip family. The combination gives Nvidia a domestic manufacturing base for AI, telecom, and high-performance computing workloads that previously required trans-Pacific shipping. TSMC has said its Arizona complex will serve as the company’s flagship US hub for cutting-edge logic, with multi-fab capacity planned through the end of the decade.
The advanced packaging gap still sends Nvidia Blackwell wafer to Taiwan for finishing
Despite the headline progress, the Nvidia Blackwell wafer does not complete its journey in Arizona. The die must still be shipped to Taiwan for CoWoS-L advanced packaging, the chip-on-wafer-on-substrate-with-locally-embedded-interconnect-connector technique that Nvidia relies on for its highest-end AI accelerators. TSMC does not yet operate a CoWoS-L line in the United States, and building one requires a multi-year capital and supplier ramp that Arizona has only just begun.
To close that gap, TSMC signed a memorandum of understanding with Amkor Technology to co-develop Integrated Fan-Out and CoWoS packaging capacity in Arizona. The line is not yet operational. Two US packaging sites are slated to begin construction in 2028, and neither will reach full operations until the early 2030s. Those facilities will focus on System on Integrated Chips (SoIC) 3D stacking and Co-Packaged Optics, not the CoWoS-L variant used by Blackwell, meaning Blackwell-class parts will continue to depend on Taiwanese packaging for the foreseeable future. Industry analysts note that advanced packaging plants take at least four years to build, owing to specialized metal bumping infrastructure and a materials supply chain that does not yet exist at scale in the US.
The packaging build-out will create a substantial supplier pipeline. CoWoS equipment vendors, high-bandwidth memory assembly partners, and package substrate makers are positioning for new US orders as TSMC’s Arizona packaging footprint takes shape. CoWoS output is targeted at roughly 100,000 units per month by the end of 2026 globally, and the company typically pairs three fabs with one advanced packaging plant. Arizona’s third fab, Fab 21 Phase 3, broke ground in 2025, with a dedicated CoWoS plant expected to follow. Apple, Nvidia, and Advanced Micro Devices have been named anchor customers for the SoIC and Co-Packaged Optics capacity that will eventually come online in the early 2030s.
Nvidia’s broader US factory push and Blackwell wafer implications
Beyond wafer production, Nvidia has signaled plans to deploy its AI, robotics, and digital twin technology inside future US manufacturing facilities, an initiative executives have linked to the same Phoenix milestone. The company has framed its domestic factory investments as a way to harden supply chains for AI hardware at a time when compute scarcity is reshaping customer procurement strategies. For TSMC, the Blackwell wafer validates a decade-long bet on Arizona as a second advanced manufacturing pole outside Taiwan, even as the packaging side of the equation remains unresolved. The Nvidia Blackwell wafer at Phoenix is therefore a milestone with a long tail, and the Nvidia Blackwell wafer will dominate supply-chain planning through the end of the decade as advanced packaging capacity catches up.
The combined effect is a US semiconductor footprint that is real but incomplete. Logic production has arrived in Phoenix; advanced packaging for Blackwell still waits in the wings. Until the Amkor-linked CoWoS and SoIC lines reach full operations in the early 2030s, the Nvidia Blackwell wafer will keep crossing the Pacific on its way to a finished AI accelerator, a reminder that the first US-made Blackwell wafer is a milestone, not the finish line.
Beyond the immediate Nvidia Blackwell wafer milestone, the Phoenix ramp sets the pace for Nvidia’s broader product cadence through 2027. The next-generation Rubin architecture, expected to tape out at TSMC’s Arizona fab in the second half of 2027, will inherit the same volume-production playbook the Nvidia Blackwell wafer line is now running, and Nvidia’s supply-chain partners are already staffing around that schedule. For customers buying large Nvidia Blackwell wafer allocations through 2026 and 2027, the practical effect is that US-based hyperscaler buyers — Anthropic, OpenAI, xAI, Meta, Microsoft — now have a confirmed domestic wafer footprint as a hedge against Taiwan-strait disruption, even if the back-end packaging step still travels through Taiwan for several more years.
Source: Tech in Asia