SK Hynix CXL Hybrid Memory XCENA MX1 debuted at the South Korean memory giant’s summit booth inside the San Jose McEnery Convention Center during OCP Global Summit 2026, which ran October 12-15. The product, built around South Korean fabless startup XCENA’s MX1 silicon, is the industry’s first commercial CXL 3.2 computational memory device, and analysts at the show floor read it as the clearest signal yet that compute express link memory has crossed from conference demonstration into commercial ingredient.
XCENA, founded in 2022 as MetisX by veterans of Samsung Electronics and SK Hynix and later rebranded, closed a $135 million Series B at a $570 million valuation on May 29, 2026, bringing total funding to $185 million. The OCP unveil gave the company two of the three largest DRAM makers publicly aligned with its architecture by close of show: SK Hynix via its hybrid memory SKU, and Samsung Electronics via a co-authored agentic AI memory blueprint set for mass production on Samsung foundry lines by the end of 2026, with revenue projected from 2027.
SK Hynix CXL Hybrid Memory XCENA MX1: Inside the Architecture
The MX1 is a CXL 3.2 Type 3 device that exposes attached memory to the host CPU as byte-addressable capacity, and that single design choice is where the architectural argument begins. It connects via a PCIe 6.0 dual x8 interface, a topology decision rather than a pure bandwidth doubling, and supports up to 2 TB of DDR5 spread across four memory channels using 256 GB DIMMs at two per channel. Standard C, C++, and Rust toolchains compile directly via LLVM, meaning no proprietary assembly is required to port workloads onto the device.
The defining feature sits in the controller: 3,072 custom RISC-V cores organized into 96 clusters of 32, each cluster sharing an L2 cache and a data translation lookaside buffer. The cores ship with FP32 and FP16 vector units, and the configuration amounts to a near-data processing engine rather than a smart controller managing passive memory. That is the bet versus competing offerings such as Astera Labs’ Leo family and Marvell’s Structera X 3406 and X 3506, the latter announced on October 12, both of which use Arm cores for orchestration rather than an autonomous compute fabric inside the memory device itself.
Two live demonstrations made the architecture legible. The first showed multiple inference servers drawing from a single shared KV cache held in a CXL memory pool, eliminating redundancy across machines. The KV cache, for context, is the structure that stores the tokens a language model has already processed so responses can be generated without recomputing prior context. The second demonstration covered retrieval-augmented generation, where the MX1 ran vector search directly inside the memory device using its embedded RISC-V cores, keeping embedding lookups off the host CPU entirely.
Samsung’s commitment arrived in the form of a co-presentation on October 15 by chief product officer Harry Kim alongside Samsung engineers, in a session titled Disaggregated CXL Memory Architecture for Agentic AI: Dynamic Pooling, Sharing, and PNM Offloading. The joint blueprint covers dynamic memory pooling, sharing across disaggregated hosts, and offloading of processing-near-memory operations into the MX1, and Samsung’s foundry commitment to mass production at the end of 2026 turns a reference design into a shipping part number over a single quarter.
The architectural stakes for the broader AI infrastructure stack are substantial. Today, KV cache duplication across inference servers is one of the largest line items in agentic-AI serving cost, and the inability to do efficient shared-memory pooling across DRAM and SSD has been the bottleneck holding back cheaper long-context models. Moving the vector search and KV-cache management directly into a CXL-attached memory pool cuts the data-movement overhead, but it also means that whoever controls the memory controller IP — in this case XCENA — captures the strategic upstream position analogous to what Nvidia holds on the GPU side. Astera Labs and Marvell are pursuing the same opportunity with Arm-based controllers; the open standards framing at the OCP panel suggests the industry is preparing for multi-vendor rather than single-supplier provisioning. The dual x8 PCIe 6.0 interface on MX1 doubles the lane count over competing CXL 2.0 controllers, which is why the OCP panel framed MX1 as a horizontal substrate rather than a vertically integrated appliance.
The SK Hynix CXL Hybrid Memory XCENA MX1 debut takes a once-experimental CXL computational memory device into a named commercial product backed by mass-production commitments from the world’s two largest memory makers, and it sets the template for how disaggregated, agentic-AI memory infrastructure will be sourced and assembled through 2027, with KV-cache deduplication, in-memory vector search, and shared DRAM-SSD pooling consolidating around a single industry-standard substrate rather than remaining bespoke per workload.
Source: https://www.techtimes.com/articles/329194/20261019/sk-hynix-debuts-cxl-computational-memory-xcena-mx1-samsung-commits-foundry.htm