The EUV tool shortage is now the defining constraint on the artificial intelligence infrastructure boom. Intel chief technology officer Pushkar Ranade says the world’s stock of chipmaking equipment would allow leading-edge wafer output to roughly double, not multiply tenfold as AI demand accelerates. Speaking during a two-day tour of Intel’s most advanced Oregon fab, published on the Dwarkesh Podcast on October 21, Ranade said ASML makes fewer than 100 extreme ultraviolet lithography machines a year. Intel, TSMC and the memory producers all compete for those systems, and most other chipmaking equipment is also in severe shortage. One TechTimes report places annual production at fewer than 70 machines.
That estimate forces a different way to think about the multi-billion-dollar fab announcements now arriving from Amazon, Microsoft, Alphabet, Meta, Intel, TSMC and Samsung. Concrete can be poured on schedule. Lithography tools cannot. Ranade’s point is not that capital has stopped mattering, but that money cannot create an EUV machine faster than ASML and its own suppliers can build one.
Why the EUV Tool Shortage Sets a Hard Ceiling
ASML produces every extreme ultraviolet lithography machine used to print the world’s most advanced chips. Its systems rely on 13.5-nanometer-wavelength light, reflective optics and a vacuum environment, and each weighs nearly 200 tons. The supply chain is narrower still. Only Zeiss can manufacture the multilayer mirrors at the required optical precision, and only Oxford Instruments provides certain synchrotron light source components.
The delivery numbers explain why the ceiling exists. ASML delivered 44 standard EUV systems in 2025 and targets roughly 65 Low-NA EUV shipments for 2026, an increase of about 50 percent. Guidance for 2027 calls for at least 80 units. An independent analysis of ASML’s first-quarter 2026 results noted that this trajectory implies EUV wafer capacity roughly doubling from the 2025 base, consistent with Ranade’s assessment. The arithmetic does not approach tenfold.
Timing compounds the limitation. An EUV system ordered today takes roughly 18 months to arrive, according to Ranade, placing today’s orders into 2028. Installation and calibration then follow delivery, and competitive manufacturing yields above 80 percent generally require another 18 to 24 months of process optimization. A fab announcement therefore precedes productive output by years that no amount of funding compresses.
Intel’s CEO Lip-Bu Tan said on Intel’s April 2026 earnings call that advanced wafer capacity was in short supply and global semiconductor supply was not keeping pace with accelerating demand. That statement came even as Intel ramped one of the world’s largest advanced-node fabs. New capacity helps, but only as fast as the tools arrive and qualify.
The Bottleneck Tightens With Every Node
The limit becomes more restrictive as chip designs shrink. Advanced chips require multiple EUV exposures per layer, and the exposure count generally rises with each process generation. The cause is physical. EUV produces stochastic defects because only a limited number of photons strike the resist at any instant, with failure rates rising exponentially as features shrink.
Fabs respond in two main ways. They can raise the dose, which reduces throughput, or use double and triple patterning, which multiplies the machine hours required per finished wafer. Both approaches make each more advanced AI accelerator consume more EUV capacity than its predecessor. The effective ceiling for wafer-equivalent accelerator output is therefore not fixed. It declines relative to what the newest chips require.
That makes Ranade’s global estimate generous for the frontier. His roughly twofold ceiling applies to the overall tool base. For processors built on the newest process nodes, where each wafer needs more exposure time and tighter defect control, the practical limit is lower. The industry’s most advanced products face the tightest version of the same problem.
Why More Fabs Do Not Automatically Mean More Chips
The industry has committed enormous sums to new fabrication plants. Amazon, Microsoft, Alphabet and Meta are collectively on track to spend approximately $725 billion on capital expenditures in 2026, much of it aimed at AI infrastructure. Accelerator purchases typically account for 30 to 40 percent of data center capital spending, pointing to demand that greatly exceeds what ASML’s delivery schedule can satisfy.
A leading-edge factory without lithography systems is a building. The tools arrive on ASML’s schedule, installation takes months, calibration takes additional months, and usable output follows a long yield-optimization cycle. Ranade also pointed to a second constraint once a process such as Intel 18A is set: the factory needs the exact tools for which the process was designed. Intel expects to reuse about 80 percent of its 18A tools for the following 14A node, but the transition still depends on a coordinated supplier chain.
His core argument is simple. Unless every supplier produces more, output cannot increase as much as AI compute demand requires. Ranade noted that AI compute has grown roughly threefold per year for the past decade, and that any acceleration would require equipment makers, their suppliers and their sub-suppliers to move together.
The Constraints Beyond Lithography
Even a dramatic increase in EUV output would not unlock unlimited production. Other bottlenecks wait behind the lithography step. Cleanroom capacity, process gases, ultra-pure water systems, photomasks, advanced packaging tools and trained operators all have to expand in step. Industry data indicates that leading-edge logic, DRAM and advanced packaging are operating at effectively full utilization, constrained by tools and physical cleanroom floor space.
Memory compounds the pressure. High-bandwidth memory, the stacked architecture that feeds AI accelerators, consumes roughly three to four times the wafer area of standard DRAM for the same delivered memory. More demand for accelerators therefore creates additional demand for wafer area used in memory production, even when the HBM itself does not appear in an accelerator company’s capital budget.
Workforce is another limit. Specialist roles in optics, vacuum systems, materials and process engineering take years to develop. Ranade’s tour also illustrated how a process must be designed around the tools available. Intel process development chief Chris Auth said 18A initially lacked a process design kit, the customer design infrastructure required to manufacture chips at a foundry, while 14A will have one from the start.
Intel’s Position Inside the Constraint
Ranade’s comments carry unusual weight because Intel is both a major advanced-node manufacturer and a major buyer of the tools he described. He holds a PhD in engineering from the University of California, Berkeley, and spent more than 17 years in two tenures at Intel developing process integration for the company’s 65-nanometer, 45-nanometer and 22-nanometer nodes. He became chief technology officer in 2024 and also serves as chief of staff to CEO Lip-Bu Tan.
Intel installed an EXE:5200B High-NA EUV system in late 2025 for its 14A process, with a cost upward of $380 million per machine. Intel and ASML announced in September 2026 that the company had processed more than one million wafers on High-NA tools, more than the rest of the industry combined. ASML CEO Christophe Fouquet described Intel Foundry as one of the industry’s leaders in adopting High-NA.
Intel also broke ground in July 2026 on a Santa Clara expansion designed to produce EUV photomasks for its 18A-P and 14A processes. Its Fab 52 in Chandler, Arizona, is designed for more than 10,000 Intel 18A wafer starts per week at full ramp, with volume production on 14A targeted for 2028. Those investments address capacity, but they do not accelerate the supplier of the core lithography systems.
Auth’s comments add a practical discipline. Intel now limits how much new technology enters a single node so it can protect delivery schedules, using phase gate reviews with yield, defect and performance criteria before features advance. The lesson from earlier nodes, including the difficult 10nm transition, is that ambition without ready tools transfers risk to process engineers and delays volume.
Intel is also working with Elon Musk on the planned Texas fab project associated with Tesla and SpaceX, and Ranade said building a semiconductor plant is far more intricate than building a car. That same complexity explains why a new fab announced today cannot relax the EUV tool shortage. It adds another customer to a queue whose order books already stretch years into the future.
The practical conclusion is that AI infrastructure will expand at the speed of the lithography supply chain, not the speed of announced capital budgets. Ranade’s estimate that output can roughly double still represents a major expansion, but the EUV tool shortage means even that outcome requires coordinated gains across ASML, its component suppliers, fab operators and advanced packaging providers. For the AI buildout now underway, the ceiling is set by tools, and the tools arrive on a schedule no factory announcement can rewrite.