Google introduced TPU 8tx and TPU 8i Max on November 9, 2026, expanding its eighth-generation Tensor Processing Unit portfolio with systems aimed at secure inference and large-scale context processing. TPU 8tx is optimized for secure and confidential inference and is also good for small-scale training, while TPU 8i Max targets massive context windows and the highest compute density per rack. Google said this is the first time it has introduced four TPU systems in a single year.
The announcement follows Google’s April introduction of TPU 8t for large-scale training and TPU 8i for real-time reasoning. Google said TPU 8t and TPU 8i offer up to 2.7 times better training performance and 80 percent better inference price performance versus the previous generation. The new systems extend that specialization. Google described TPU 8t as the scale-up training platform, TPU 8i as the low-latency reasoning engine, TPU 8tx as the confidential computing option, and TPU 8i Max as the massive-context and rack-density platform.
TPU 8tx: Confidential computing moves into the accelerator
TPU 8tx uses the same underlying silicon as TPU 8t, with 12.6 PFLOPs of native FP4 compute and 216GB of HBM3e memory. Unlike TPU 8t, which is paired with Google’s own Axion ARM hosts, TPU 8tx is paired with custom AMD CPU hosts. Google said the system builds a secure enclave into the hardware layer, keeping data and model weights protected and isolated even while they are in active use.
Google said the design is intended for regulated enterprises and governments running frontier or proprietary models and autonomous agents alongside sensitive information. The company said teams can fine-tune models with private data, distill large models into smaller ones and train agents through reinforcement learning without migrating data between separate clusters. TechTarget reported that this lets a bank or government agency run those tasks on one confidential system without moving sensitive data between clusters.
The system also adopts the low-latency Boardfly interconnect architecture. Google said that design limits single Pod configurations to 1,152 chips and reduces the network diameter between the furthest chips in a Pod by over 50 percent. Google says TPU 8tx delivers up to 2 times lower latency compared with TPU 8t, with a near-zero performance penalty. Amin Vahdat, Google’s senior vice president and chief technologist of AI and infrastructure, said the combination of training-grade compute and fast inference allows organizations to run and customize models on a single system.
The security emphasis reflects a broader change in enterprise AI infrastructure. Mark Lohmeyer, Google’s Cloud vice president and general manager of compute and AI infrastructure, told TechTarget that AI requirements now extend beyond raw compute to data movement, memory efficiency, latency, cost and security at scale. Patrick Moorhead, founder and chief analyst of Moor Insights and Strategy, wrote to TechTarget that roughly two-thirds of AI compute now goes to inference, making specialized inference hardware a logical priority. The TPU 8tx therefore combines a training-oriented chip with controls intended to address enterprise data sovereignty requirements.
Density is the central TPU 8i Max feature
TPU 8i Max is built around two low-latency TPU 8i chips combined on one package. Google said the system delivers double the compute, double the SRAM and double the high-bandwidth memory of TPU 8i. It provides 20.1 PFLOPs of FP4 inference power, 384GB of HBM3e capacity, 768 MB of on-chip static RAM and 17.2 TB/s of high-bandwidth memory bandwidth. TPU 8i has 288GB of HBM3e memory and 384M of on-chip VMEM, compared with 384GB of HBM3e and 768M of on-chip VMEM for TPU 8i Max.
Google said TPU 8i Max fits twice the silicon within the existing rack footprint. That allows data centers to deploy more computing power per square foot and per watt. The strategy addresses the memory bottleneck that appears when multiple agents work across large codebases or long media files, where bandwidth for storing KV caches becomes a constraint. More on-chip memory reduces the need to move data between processors, which can lower latency and reduce the power required for an AI model to process information.
The context target is substantial. Google said it developed TPU 8i Max alongside work on massive context windows for its Gemini frontier model, which supports a 1 million-token context window. Google described that capacity as roughly 750,000 words or 1,500 pages of text. Smaller models often support context windows between 128,000 and 256,000 tokens. TPU 8i was already designed to cut inter-chip communication delays by up to half, and the Max configuration extends that low-latency foundation with more compute, memory and bandwidth.
Software is central to the strategy
Google is pairing the hardware with changes intended to lower adoption barriers. It has open-sourced TorchTPU, allowing PyTorch code and Hugging Face models to run natively on TPUs. Google is also open-sourcing TPU Sync, a model-state layer that combines chip memory, host memory, shared storage and the network into a single memory hierarchy. The company said TPU Sync can tier KV caches off the chip, stream context across disaggregated prefill and decode nodes, and synchronize reinforcement learning weights, reducing KV transfer latency and Time to First Token by more than 90 percent.
Two orchestration tools are now generally available on Google Kubernetes Engine. Cloud Pathways lets customers orchestrate large-scale TPU systems from a single controller. GKE dynamic slicing uses optical circuit switching to assemble or partition TPU topologies on demand. Google said dynamic slicing can cut job startup times by up to 5 times and accelerate fault recovery by up to 4.5 times.
Google’s Agent Compute Engine suspends idle accelerators while AI agents are paused and shifts working memory off the chip in milliseconds. Google said this approach reduces infrastructure costs when agents wait for a database lookup, an external software tool or human feedback. The company also open-sourced an XLA Serving Engine that can train models in Python and serve them directly from a low-latency C++ runtime across TPUs, GPUs and CPUs.
A faster hardware roadmap
Google said its TPU release cadence has accelerated from one release every two years to one per year and then to four specialized systems. The company credits its modular AI Hypercomputer architecture for allowing it to adjust packaging, high-speed memory, optical networking and security without waiting for an entirely new chip design cycle. Google said this system approach can produce specialized configurations in months rather than years. The company also said it uses AlphaChip reinforcement learning and Gemini models to complete chip layouts in hours rather than weeks.
Adoption is already broadening. Google said more than 100 customers and partners, including frontier labs, trading firms, retailers and universities, are using TPUs. Anthropic will expand its use of next-generation TPUs beginning in 2027, while the California Institute of Technology has shifted some of its cancer research from its own high-performance computing system to Google Cloud TPUs, according to Moorhead.
Commercial details remain limited. Google did not provide availability dates or pricing for TPU 8i Max and TPU 8tx. The earlier TPU 8t and TPU 8i systems are still due to go online by the end of 2026. The open strategic question is whether the added density and hardware-level security will outweigh the cost of moving enterprise workloads into specialized systems before clear pricing and deployment schedules are available. For now, TPU 8tx gives Google a distinct answer for confidential inference, while TPU 8i Max targets the increasingly memory-intensive workload created by million-token contexts and fleets of collaborating agents.