Advanced chip packaging has become the binding constraint on artificial intelligence hardware, and on November 6, 2026 Reuters reported that the race to build AI infrastructure is unleashing billions of dollars of investment into a once unglamorous stage of manufacturing that now decides how many powerful processors the industry can actually ship. Advanced chip packaging links separate pieces of silicon, such as processors and memory chips, on a shared base so they can work together at high speed. The technique matters most for AI chips that need to move vast amounts of data between processors and nearby memory. Faster transfers can accelerate both the training and running of AI models.
The scale of the shift is captured by two separate forecasts. Yole Group expects revenue from advanced packaging to overtake the traditional route for the first time in 2026, with capital spending on the technology expected to near 28 billion dollars. Pat Gelsinger, the former Intel chief executive now a partner at Playground Global, estimated that advanced packaging could eventually account for as much as half the value of a chip product. His view reflects a broader shift toward heterogeneous designs in which some graphics and central processing units integrate 10 or more chips, sometimes as many as 20.
advanced chip packaging: TSMC’s CoWoS capacity sets the pace
The bottleneck sits at TSMC. The world’s largest contract chipmaker dominates the most sophisticated advanced packaging technology, including chip-on-wafer-on-substrate, or CoWoS. This process combines silicon components on a shared base and is widely used by Nvidia, AMD and Broadcom, as well as cloud companies building their own AI chips.
TSMC’s ability to expand CoWoS output matters because a leading-edge processor cannot reach customers until it has been joined to high-bandwidth memory and assembled into a package capable of handling demanding workloads. A shortage at this stage can limit shipments even when wafer production is strong. It can also force customers to redesign schedules, reallocate scarce supply and reconsider where final assembly takes place.
TSMC is not standing still. The company is developing chip-on-panel-on-substrate, or CoPoS, its own panel-based packaging technology. TSMC said it built a CoPoS pilot line in April, with production expected within a couple of years. The approach uses a larger rectangular panel instead of a round wafer, potentially increasing the number of units processed and reducing unused material as AI processors become larger and more complex.
The initiative gives TSMC a way to defend its leadership if customers diversify their assembly partners. It also puts the company into a broader race with specialists such as Powertech Technology, which believes panel-level packaging can make packaging capacity more productive. CoWoS remains the established center of the market, but CoPoS could eventually alter how suppliers think about factory footprints, tooling and materials.
Nvidia financing expands ASE supply
TSMC’s capacity limits have pushed some chip designers to look for additional supply. Nvidia is providing billions of dollars in financing to expand CoWoS packaging capacity at Siliconware Precision Industries, or SPIL, a unit of Taiwan’s ASE Technology, according to an industry executive familiar with the matter, who sought anonymity for lack of authorisation to speak to media. The executive said the funding would support new factory space and equipment, and that the scale of the support had not previously been reported.
Nvidia did not respond to a request for comment. ASE said it does not comment on market rumours involving its customers. The arrangement therefore should not be presented as a confirmed Nvidia announcement, but it points to the strategic importance of having packaging capacity outside TSMC’s own network.
For Nvidia, CoWoS supply is tied directly to the delivery of accelerator systems used to train and operate AI models. Expanding SPIL’s capability offers a potential second source and gives Nvidia greater influence over the pace of capacity additions. For ASE, the opportunity reaches beyond a single customer and into the wider outsourced assembly market. It also requires capital, qualified facilities, process expertise and enough customer volume to sustain expensive production lines.
AMD has also committed more than 10 billion dollars across Taiwan’s semiconductor industry. Its announced investments include partnerships with ASE, SPIL and Powertech on advanced packaging. The scale reflects AMD’s wider ambition to deepen its position in Taiwan while reducing potential pressure from any single packaging supplier.
Powertech targets the panel-level opportunity
Taiwan’s Powertech Technology sees the packaging squeeze as an opening. Chairman D K Tsai said in August that everyone is looking for a solution outside TSMC because they do not want to rely entirely on TSMC. Powertech is betting on panel-level packaging, which uses larger rectangular panels instead of round wafers as the packaging platform. The approach can fit more chips into each production run and waste less material as AI processors grow larger and more complex.
Powertech is working with AMD and Broadcom on the technology. The company plans to invest 400 million dollars in an advanced packaging joint venture with Broadcom in Singapore, with production potentially beginning in 2028. Senior vice president Jim Lin said the most important thing at present is capacity and that customers were waiting for Powertech to ramp up production.
The Singapore project is not an immediate answer to TSMC’s near-term CoWoS constraints because its possible production start is still years away. Instead, it represents a strategic hedge for customers seeking geographically diverse capacity and for Powertech’s attempt to become a larger advanced packaging supplier. AMD and Broadcom are also central to TSMC’s CoWoS business, making their participation in a competing route particularly significant.
Lisa Su did not directly answer whether Powertech’s panel-level packaging could offer an alternative to TSMC. She said CoWoS and advanced packaging are super important for high-performance computing and that the industry needs more capacity overall. Her comments support the need for additional supply, but they do not amount to an endorsement or rejection of panel-level packaging.
Microsoft Azure has reached a similar point of evaluation. Rani Borkar said panel-level packaging would reduce material waste, but the company has not decided whether or when to adopt it. That distinction matters because cloud operators influence large volumes of custom chip demand. An eventual adoption decision would validate panel-level manufacturing at significant scale, while continued caution would leave TSMC and other wafer-based packaging routes with more of the near-term workload.
Equipment makers prepare for a larger market
The expansion of advanced packaging is also creating opportunities for companies that supply specialized factory equipment. Applied Materials said the market could grow significantly within three to five years. Vice president Sree Kesapragada described the opportunity as near-term rather than something deferred to the end of the decade.
Packaging lines require different tools from leading-edge wafer fabs, including equipment for placing components, inspecting interconnects, managing substrates and improving yield. As packages combine more dies and more memory, the precision required at the assembly stage rises. Yield losses can therefore carry a much greater cost when a single package contains the processor, memory and supporting components needed for an AI accelerator.
Tokyo Electron is another company positioned within this broader manufacturing chain, although the reported investment plans do not assign it a specific role in the capacity projects described here. Its inclusion reflects the wider dependence of advanced packaging on specialized production equipment and process control.
Yole Group’s 28 billion dollar figure is a 2026 advanced packaging capital spending forecast, not a confirmed sum committed by the named companies in the projects discussed above. It illustrates the scale of the market response while individual investments remain at different stages of approval, construction and production.
Capacity diversification changes chip supply chains
The strategic issue is not limited to whether one factory can produce more packages. Customers also need confidence that capacity arrives with acceptable yield, reliable quality and enough supporting materials. AI demand is unusually sensitive to delay because data centers are expensive to build and operate, and processors that sit idle cannot earn back the investment made in the surrounding infrastructure.
Competition among TSMC, ASE Technology, SPIL, Powertech Technology, PTI and other suppliers should eventually give chip designers more negotiating options and reduce the risk of a single bottleneck. It may also broaden the industrial base for advanced packaging beyond Taiwan, as the Powertech and Broadcom joint venture in Singapore demonstrates. Different production platforms can also offer different tradeoffs in throughput, material use, package size and process maturity.
There are limits to treating all routes as interchangeable. CoWoS is proven in demanding applications, while panel-level packaging and CoPoS are still developing at different stages. Yield learning, equipment availability, substrate supply and customer qualification can take time. Nvidia, AMD and Broadcom are all tied to TSMC today, but their investments in external or alternative capacity suggest that they want more control over future supply.
Equipment suppliers also face a market that may expand rapidly while remaining exposed to the uneven order patterns typical of capital equipment. Tokyo Electron, Applied Materials and other suppliers can benefit from expanding production, but customers may also sequence projects differently if AI infrastructure spending changes. The immediate opportunity is strong, while the duration of the buildout remains uncertain.
The broader pattern extends beyond AI accelerators. Government-backed and sovereign technology programs are placing new emphasis on domestic semiconductor capabilities, packaging and talent. That can create additional demand for packaging expertise even if the largest near-term market remains concentrated in data center processors. A secure supply chain needs design, fabrication, assembly, testing and skilled personnel, not just leading-edge wafers.
For now, the race to add CoWoS capacity is the clearest response to the bottleneck. TSMC is developing CoPoS, Nvidia is reportedly helping finance expansion at SPIL, and Powertech is building a Singapore joint venture with Broadcom. AMD has committed substantial capital across Taiwan’s ecosystem, while Microsoft Azure is weighing the benefits of panel-level packaging without making an adoption decision. These efforts reflect a fundamental change in where the AI supply chain’s constraints are appearing, and advanced chip packaging has become the central arena for resolving them.