EVAS RISC-V just got its biggest endorsement yet. On September 18, Beijing-based AI chip startup EVAS Intelligence closed a financing round of roughly RMB 2 billion (about $295 million), one of the largest private semiconductor raises in China this year. With more than 20 institutional backers signing on, including heavyweights Huatai Innovation, Eastern Bell Capital, and a fund tied to SMIC, the deal catapulted EVAS to a post-money valuation near RMB 15 billion (approximately $2.21 billion), firmly unicorn territory.
The Architecture Behind EVAS RISC-V
Capital aside, the real story is architectural. EVAS is not licensing anyone’s silicon. Its Epoch series is built from scratch on the RISC-V instruction set, with the company’s internally developed fifth-generation RISC-V DSA, called EVAMIND, sitting on top. Where Nvidia GPUs lean on thousands of general-purpose shader cores running CUDA in a SIMT pattern, EVAS took a page from Google’s TPU playbook: matrix and tensor engines do the heavy lifting, while embedded RISC-V cores choreograph the data flow. Epoch also natively supports block-quantized FP8 precision, a milestone EVAS claims is a first for a Chinese RISC-V cloud chip. The next generation pushes further, into EXFP4 and MXFP4 microscaling formats already on the roadmap.
Why EVAS RISC-V Sidesteps Washington’s Export Net
The reason this matters politically is structural. RISC-V International, the nonprofit that governs the open instruction set, relocated from the United States to Switzerland in 2019, explicitly citing concerns about US trade regulations. A Swiss-governed ISA with more than 4,500 global members, including Google, Nvidia, Intel, and Red Hat, sits outside the reach of Commerce Department export controls in a way proprietary architectures cannot. That is the gap EVAS is building through. Where Huawei’s Ascend chips rely on a proprietary architecture with questionable resistance to US pressure, EVAS RISC-V silicon rests on an open standard whose control mechanism is fundamentally different. US lawmakers flagged this in November 2023, urging export licenses for RISC-V work with China, but no such rule has been enacted, and many observers argue trying to wall off an ISA with thousands of members would damage global research far more than it would contain Beijing.
EVAS RISC-V: From Chip to Rack: The SuperNode Play
EVAS is not selling a standalone accelerator. At the 2026 World Artificial Intelligence Conference in Shanghai, the company unveiled what it calls the industry’s first RISC-V AI SuperNode, a full-rack system integrating Epoch chips, its proprietary ELink interconnect, an orthogonal backplane-free design, and full liquid cooling. ELink pushes 3.2 terabits per second of single-chip bandwidth, sidestepping the signal-integrity wall that copper-based supernodes hit around 128 accelerators. EVAS says a single rack can host 64 to 128 Epoch chips in a symmetric Scale-Up configuration, and clusters can stretch past 100,000 cards. Strategic deals with Zhongneng Intelligent Computing and Guofu Data are already in motion to build out what the company calls the world’s first full-stack RISC-V AI Token Factory.
Software, Benchmarks, and the Open Questions
The software stack could decide whether this architecture translates into real deployments. EVAS’s EVACA platform and KernelFab engine use AI agents to compress custom operator development from weeks to days, while a VISA virtual instruction set promises write-once portability across chips, a direct answer to CUDA lock-in. It is a credible counter-narrative. It is also, for now, largely a company narrative. No independent third-party benchmarks have verified EVAS’s performance claims, and the dense silicon-to-rack scaling story rests on engineering assumptions that have not been stress-tested in production cloud environments. The raise gives EVAS RISC-V the runway to prove it. The architecture choice gives it a path US export controls were specifically designed to close. Whether that path holds depends on what ships, what gets measured, and whether Washington decides the open-standard loophole is finally worth closing.
The fresh capital lands EVAS RISC-V into a semiconductor landscape already crowded with well-funded challengers. SiFive, Tenstorrent, and Esperanto have collectively pulled in over a billion dollars from backers eager to commercialize open-standard cores, while Qualcomm’s recent automotive RISC-V disclosures and Nvidia’s investment in RISC-V ecosystem tooling signal that even incumbent x86 and Arm-aligned players are hedging their architectures. Meanwhile, hyperscalers continue to anchor demand for custom silicon, with cloud providers spending an estimated $60 billion on AI accelerators in 2025, and a growing share of those designs now incorporating RISC-V controller and management cores to sidestep Arm licensing frictions. Foundry capacity remains the gating factor, with TSMC’s advanced nodes effectively fully booked through 2026, complicating the supply chain calculus for any startup that needs leading-edge wafers to be competitive. EVAS’s vertical integration story will be judged against these realities, where execution speed, not architectural purity, increasingly determines who captures the next wave of sovereign-AI and confidential-compute workloads.