High-NA EUV moved from a roadmap promise to a high-volume manufacturing reality this week as ASML used the SEMICON Taiwan 2026 stage to confirm that ten High-NA EUV systems are now in production at four customer sites, with three additional tools either shipping or completing installation. The disclosure, reported by TrendForce citing Economic Daily News coverage of the event, marks the most concrete signal yet that the 0.55-NA platform is no longer a research curiosity but a working engine of leading-edge silicon. For an industry that has spent nearly a decade debating whether High-NA EUV would arrive in time to matter, the operational footprint announced in Taipei suggests the answer is now decisively yes.
Intel Panther Lake: First Logic Product in High-NA Volume
The headline customer milestone belongs to Intel, which has deployed High-NA EUV in HVM for select Core Ultra Series 3 processors, codenamed Panther Lake and built on the Intel 18A process. According to Storm Media reporting cited by TrendForce, Panther Lake is the first logic product anywhere to enter volume production using the technology, a claim that carries significant symbolic weight given Intel’s broader foundry ambitions. Shipping a consumer-class part through a High-NA EUV-enabled flow validates that the lithography, metrology, and supply-chain ecosystem around 0.55-NA can sustain the tolerances required for high-volume logic. For Intel, it is also a credibility moment: Core Ultra Series 3 becomes a proof point that Intel 18A is not merely a process node on paper but a manufacturing reality anchored by the most advanced patterning tool ever commercialized.
The Productivity Roadmap: From 135 WPH to 250+ WPH
Throughput has long been the swing factor for High-NA EUV economics, and ASML’s updated productivity curve is the single most important data point for fab planners. The qualified EXE:5200B has demonstrated 135 wafers per hour in acceptance testing using what ASML calls AB mode. From that baseline, the EXE:5200C is positioned at 160 WPH, followed by the EXE:5200D at 175 WPH. By the end of the decade, the EXE:5400E is targeted at 180 WPH, with AA mode projected to exceed 210 WPH on the same generation. Beyond that, a higher-productivity successor designated EXE:5600 is aiming for 250+ WPH, though ASML has not yet committed to a firm HVM introduction window.
For cost-of-ownership modeling, the practical takeaway is that wafer pass cost on High-NA EUV tools will improve by roughly 33% from the current 5200B to the 5400E within the same decade, before stepping up another ~40% to the 5600 platform. That trajectory is what allows High-NA EUV to displace multi-patterning strategies on critical metal and via layers, where today the industry tolerates three or four lithographic exposures to achieve sub-30 nm pitches. As throughput rises, single-exposure High-NA EUV becomes the lower-cost option, not the premium one.
Why 0.55-NA Changes the Cost Curve
The core technical argument for High-NA EUV is resolution. A higher numerical aperture shrinks the printable pitch in a single exposure, which means more layers can be patterned without resorting to double, triple, or quadruple patterning with conventional 0.33-NA EUV. Each removed patterning step eliminates lithography, etch, deposition, and metrology cycles, compounding into meaningful cycle-time reductions and defect-rate improvements. ASML disclosed that its installed High-NA EUV fleet has collectively exposed more than 1.35 million wafers, a useful proxy for process maturity and recipe convergence across customer flows.
For memory, the implications are equally significant. TrendForce notes that High-NA EUV’s imaging characteristics could support up to five future 2D DRAM process nodes, an unusually long technology runway. SK hynix installed an EXE:5200B tool at its M16 fab in the second half of 2025 as the first mass-production development step for DRAM, and Samsung is publicly targeting a 1nm logic process around 2030 on the High-NA EUV platform. Both moves suggest the memory industry views High-NA EUV as a strategic hedge against the diminishing returns of multi-patterning on conventional EUV.
ASML Pricing Power and the UBS Upgrade
The operational progress has not gone unnoticed on Wall Street. UBS recently raised its ASML price target to €2,350 from €2,250, citing two factors that map directly onto the SEMICON Taiwan disclosures: pricing power on a tool family with no commercial alternative, and expanding memory exposure as DRAM customers adopt High-NA EUV for advanced nodes. With Samsung and SK hynix both publicly engaged and ten tools already running in logic, the addressable market for ASML’s High-NA EUV revenue is wider than the consensus model assumed even six months ago.
What High-NA EUV Means for the Leading-Edge Roadmap
The near-term beneficiaries are the foundries and IDMs with the capital depth to absorb a single-tool price tag north of $350 million. Intel has staked its Intel 18A node and Panther Lake credibility on early High-NA EUV adoption, and TSMC is widely expected to follow as its A14 and A10 process flows mature. Samsung’s stated 2030 logic target implies the technology will underpin at least three to four process generations in the next decade, an unusually long planning horizon for any single lithography platform.
For investors, the inflection point to watch is not the next tool shipment but the next productivity upgrade. Each step from 5200B to 5400E lowers wafer pass cost and broadens the set of layers where High-NA EUV is the cheapest option. Once the EXE:5600 crosses 250 WPH, the case for single-exposure High-NA EUV becomes economically overwhelming on most critical layers, and the industry’s leading-edge cost curve shifts materially.
The Bottom Line for Semiconductor Strategists
ASML’s SEMICON Taiwan 2026 disclosures effectively close the chapter on whether High-NA EUV works and open the chapter on how fast it scales. Ten systems in production at four customers, 1.35 million wafers exposed, and a credible roadmap to 250+ WPH by the end of the decade form the strongest commercial case the technology has yet seen. Intel’s Panther Lake has proven that High-NA EUV can ship in a consumer logic product. Memory adoption is no longer a question of if but when. The High-NA EUV era has begun, and it is reshaping the economics of leading-edge silicon faster than most forecasts anticipated.
Source: ASML Advances High-NA EUV Toward HVM as 10 Systems Reportedly Go Live at 4 Customers