The Maia 300 Ambition Runs Through CoWoS
Why Packaging Capacity Trumps Chip Design
Maia 200 Sets the Architectural Blueprint
The Competitive Pressure Behind the Order
Maia 300 Microsoft is negotiating with Taiwan Semiconductor Manufacturing Co. to lock in production capacity for more than 300,000 units of its next-generation Maia 300 AI accelerator, with delivery targeted for 2027 and a public reveal planned as soon as September, according to reporting from The Information cited by Reuters on August 10, 2026. The ambition is substantial, and so is the obstacle standing in its way: every AI accelerator on the market depends on a single advanced packaging process controlled exclusively by TSMC, and the queue for that process is already dominated by Nvidia.
The Maia 300 Ambition Runs Through CoWoS
Before any AI accelerator chip can ship, it must complete a final assembly step called CoWoS, or Chip-on-Wafer-on-Substrate, a 2.5D packaging technology developed by TSMC. The name describes the physical stack: the logic die and multiple stacks of High Bandwidth Memory are bonded to a silicon interposer, then mounted on an organic substrate that connects the assembled module to a server board. The silicon interposer provides the high-density copper routing that carries signals between logic and memory at the bandwidth modern AI models require, measured in several terabytes per second. No organic substrate can replicate that density, and there is no merchant market for CoWoS modules. The assembly runs captive at TSMC advanced packaging facilities in Taiwan, with additional capacity ramping at TSMC Arizona.
Why Packaging Capacity Trumps Chip Design
CoWoS capacity is the single binding global supply constraint on the AI accelerator market. Every Nvidia H100, H200, B100, B200, GB200, and Rubin-generation GPU ships on CoWoS. Every AMD MI300 and MI400 series accelerator ships on CoWoS. Google’s TPU, Amazon’s Trainium, and Microsoft’s existing Maia line all depend on the same allocation. TSMC CEO C.C. Wei told shareholders in June 2026 that CoWoS capacity remains sold out through 2026, with assembly lead times running 52 to 78 weeks across most of the company’s advanced-packaging facilities.
TSMC has been doubling CoWoS capacity annually since 2023, scaling from roughly 35,000 wafers per month in late 2024 toward a projected 130,000 by the end of 2026, and demand has consistently outrun that expansion. Within that constrained pool, Nvidia alone holds approximately 60 percent of TSMC’s CoWoS allocation, roughly 595,000 wafers of an estimated one million wafers of 2026 demand. The top three customers, Nvidia, Broadcom, and AMD, account for more than 85 percent of total capacity. Microsoft’s 300,000-unit Maia 300 order would have to be carved out of the remaining 15 percent, competing with every other hyperscaler custom chip program, every Broadcom ASIC customer, and every AI chip startup still seeking a reservation. J.P. Morgan analysts have flagged that projects concentrated on TSMC’s N3 manufacturing process and CoWoS packaging face supply tightness through 2027, a constraint directly relevant to the Maia 300 ramp.
Maia 200 Sets the Architectural Blueprint
The scale of the Maia 300 ambition is best understood by comparison to what came before it. Microsoft’s second-generation Maia 200, unveiled in January 2026 on TSMC’s 3-nanometer process, was produced in the tens of thousands of units. The Maia 300 order being negotiated represents an order of magnitude more. Microsoft’s ultimate production target is capacity for more than one million units, according to the same reporting, though component supplies and ongoing packaging negotiations could constrain that figure.
Andrew Wall, general manager for Microsoft’s Azure Maia, has offered the company’s frame for that ambition without confirming any specific production figure. “We expect our Azure Maia deployments to support AI workload demand measured in gigawatts,” he told reporters on August 10. Data centers requiring several gigawatts of power draw would need millions of AI processors, making the gigawatt framing a way of describing the program’s long-run scope without committing to a number TSMC has not yet agreed to produce.
The Maia 200’s technical profile is well-documented. The inference-first chip contains more than 140 billion transistors, with 216 gigabytes of HBM3E memory providing 7 terabytes per second of memory bandwidth, and 272 megabytes of on-chip SRAM, more than Nvidia’s Blackwell GPU carries at 192 megabytes, according to Microsoft’s Azure Maia chief. It delivers more than 10 petaFLOPS at FP4 precision and roughly 5 petaFLOPS at FP8, within a 750-watt thermal design budget. The chip has been running in Microsoft’s data centers in Arizona and Iowa since early 2026, handling inference for OpenAI’s GPT-5.2 and Microsoft 365 Copilot. Microsoft has said it delivers more than 30 percent better performance per dollar than the previous generation, a figure Satya Nadella cited at the company’s Q4 FY2026 earnings call in July. Discussions with Anthropic for Claude inference workloads on Maia 200, confirmed in May 2026, remained unresolved as of this writing. Marvell is reportedly the chip engineering partner.
The Competitive Pressure Behind the Order
The urgency behind the 300,000-unit order is in part a response to how far ahead the competition has gotten. Google began recognizing revenue from direct sales of its Tensor Processing Units in the quarter ended June 2026, a milestone Microsoft’s chip program has not reached. Amazon’s Trainium chips have been gaining traction with customers, and Amazon’s custom silicon business spanning Graviton, Trainium, and Nitro crossed a $20 billion annual revenue run rate in early 2026. Microsoft’s Maia program has moved more slowly: the first-generation Maia 100 shipped in limited volume after its 2023 announcement, Maia 200 was delayed and reached mass production only in January 2026, and the chip remains confined to two US data centers.
In response to the 300,000-unit reporting, Wall issued a statement notable for what it declines to deny. “Microsoft continues to invest in custom silicon as part of our long-term AI infrastructure strategy. While we don’t share production volumes, the figures reported don’t reflect the scale of our program,” he said in remarks reported by Reuters. TSMC did not respond to requests for comment. The Maia 300 September reveal, if it materializes, will arrive before Microsoft has answered whether its second-generation silicon can serve an external frontier model at production scale, and the program’s long-term ceiling will ultimately be defined less by chip design than by access to CoWoS capacity shared with Nvidia, where Microsoft is still negotiating for its Maia 300 allocation.Source: TechTimes (William Chan), reporting from The Information via Reuters, August 2026.