Abstract semiconductor wafer and circuit geometry representing TSMC revenue growth from AI chip demand

TSMC’s July Revenue Climbs 45% as Nvidia, AMD, and Apple Drive AI-Chip Demand

TSMC reported July 2026 revenue of NT$467.58 billion, roughly $14.5 billion, a 44.7% increase from the same month a year earlier. The figure extends a run of record-breaking monthly prints from the Taiwanese foundry and underscores how AI-related demand from Nvidia, AMD, Apple, and Broadcom continues to define the company’s growth trajectory. For the first seven months of the year, TSMC has now generated approximately $89.1 billion in revenue, running 37% ahead of the comparable 2025 period.

The monthly print is consistent with TSMC’s second-quarter results, released in mid-July, where revenue hit roughly $40.2 billion and net profit climbed 77.4% year-over-year to a record NT$706.56 billion. Gross margin reached 67.7%, above the top end of management’s guidance. For the third quarter, TSMC expects revenue between $44.6 billion and $45.8 billion, which would translate to roughly 47% year-over-year growth. The company has also raised its full-year 2026 capital expenditure outlook to a range of $60 billion to $64 billion, up from a previous ceiling of $56 billion, and committed an additional $100 billion to its Arizona fabrication project on top of $165 billion already pledged.

High-performance computing, the segment that houses AI accelerator production, accounted for 66% of TSMC’s second-quarter wafer revenue, up from 60% a year ago. Smartphones, once the company’s largest revenue driver, now represent 22%. The mix shift reflects a structural change in semiconductor demand: the largest buyers of leading-edge silicon are no longer phone makers chasing annual upgrade cycles but cloud hyperscalers and AI infrastructure operators deploying compute for training and inference.

TSMC: 3nm and 2nm capacity is the binding constraint

TSMC’s advanced nodes are now the bottleneck for the entire AI buildout. The 3-nanometer process contributed 30% of wafer revenue in the second quarter, while the 5-nanometer node added 33%. Combined production at 7nm and below represented 77% of all wafer revenue, the highest concentration at the bleeding edge in the company’s history. Demand for advanced packaging, particularly TSMC’s chip-on-wafer-on-substrate (CoWoS) technology used to stack high-bandwidth memory alongside AI accelerators, remains tight, with order books extending well into 2027.

Customers are also locking in capacity on the upcoming 2-nanometer node. Nvidia, AMD, and Apple are all positioned as anchor customers for N2, with risk production already underway and high-volume manufacturing expected to ramp through 2026 and into 2027. The combination of N3, N5, and N2 demand has left TSMC’s most advanced fabs fully booked, and management’s decision to raise capital expenditure mid-year signals that those orders continue to extend further into the future than previously expected.

What the demand signals mean for Apple’s silicon roadmap

For Apple, the capacity picture directly shapes the Mac and iPhone product cycles. The company is reportedly skipping its M6 Pro, M6 Max, and M6 Ultra chips to accelerate the M7 family, which is expected to debut as early as spring 2027. According to Bloomberg reporting, the M7 generation is designed to bring major neural-engine upgrades aimed at on-device AI workloads, with the M7 Ultra rumored to support up to 1.5TB of unified memory. Pulling the M7 launch forward is a bet that Apple can secure enough N3 and N2 capacity at TSMC to support both the redesigned MacBook Pro line and the iPhone 18 cycle without disrupting the broader iPhone production schedule.

TSMC’s relationship with Apple is also evolving. With HPC now consuming two-thirds of TSMC wafer output, Apple’s A-series and M-series processors compete for the same fab space as Nvidia’s data-center GPUs and AMD’s MI-series accelerators. The capacity crunch effectively forces Apple to choose between volume on its existing nodes and reserving early access to N2, and the M7 acceleration suggests Apple has prioritized the latter.

Nvidia and AMD product roadmaps hinge on the same fabs

The same capacity dynamics shape Nvidia and AMD’s accelerator roadmaps. Nvidia’s Blackwell and next-generation Rubin GPUs are both produced at TSMC’s advanced nodes, and the company has been one of the largest consumers of CoWoS advanced packaging. AMD’s MI-series accelerators, including the MI300X and MI350, share the same foundry footprint. With TSMC’s 3nm capacity running near full utilization and 2nm slots allocated years in advance, both Nvidia and AMD are likely to compete on packaging throughput and yield improvements rather than node migration frequency.

Analysts have noted that this dynamic tightens the link between TSMC’s monthly revenue prints and the broader AI infrastructure cycle. The PHLX Semiconductor Index sold off more than 23% from its June peak through mid-July, shedding over $1 trillion in market value amid concerns that AI capital expenditure was outrunning revenue returns. TSMC’s July data, showing acceleration rather than deceleration, pushes back against that bearish narrative. Year-to-date, TSMC shares listed in Taiwan have risen approximately 50%, more than double Nvidia’s roughly 20% gain, reflecting investor preference for the diversified foundry exposure over single-product concentration.

TSMC controls roughly 73% of the global advanced foundry market, and the July numbers reinforce the view that the AI chip supply chain is operating closer to a shortage than a surplus. With the world’s largest technology companies now committing more than $830 billion in cumulative AI infrastructure spending over the next three years, the limiting factor for the cycle is no longer demand but how quickly TSMC can convert its raised capital expenditure into shipped wafers. For Nvidia, AMD, Apple, and the broader hyperscaler customer base, the answer increasingly depends on monthly revenue prints from a single Taiwanese chipmaker.

Leave a Comment

Your email address will not be published. Required fields are marked *